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The NetFPGA USB2.0 Interface board is intended to mount to the 40-pin debug connector of a NetFPGA 1G network board to provide 2 x USB2.0 Interface device ports which are configured to appear to USB 2.0 host devices (such as SoCs) as a USB-attached Network Interface using the USB Communications class Ethernet (on Linux, this is mostly supported by the usbnet driver shim).

NetFPGA USB 2 is intended as a proof-of-concept for the USB 2 GigE switch project, itself a part of the Multi-SoC PoE Cluster project.


The CY7C68013 was initially considered, but dispelled due to a misunderstanding of the role of the 8051 core in the device. The CY7C68003 would allow a much faster (60MBps) throughput, but at the cost of significantly more complex USB2.0 logic in the FPGA. The complexity of the FPGA code has led to a re-evaluation and the choosing of the CY7C68013 device instead, and hence the v0.2 board.

Power Source

There is no provision for power supply on the Debug connector of the NetFPGA 1G (there are 6 pins for GND). Therefore a flying lead is added to the NetFPGA to pick up +2.5V and +3.3V supplies for the NetFPGA USB 2 interface board.


On Linux USB Network Interfaces are mostly supported by the usbnet driver shim, with one of several device driver layers below.

As we have access to a number of USB Ethernet adaptors using the ASIX devices, we choose to make NetFPGA USB 2 compatible with the drivers/net/usb/asix.c device driver interface.

For the v0.1 interface, the compatible implementation of a USB Ethernet device using Verilog will be USB2 Net A. For the v0.2 device, most of the initialisation is done by the integrated 8051 CPU.