Nu2 rx fifo 4kx18 to 72

nu2_rx_fifo_4kx18_to_72 is a Verilog module which implements an asynchronous NetFPGA FIFO for receiving 16-bit USB OUT data from the NetFPGA USB 2 v0.3 interface and presenting it to the NetFPGA Reference Design frameworks User Data Path as 64+8 bit data.

This module is used exclusively by the two nu2_rx_queue modules, which instantiate one copy each.