PoE Compute Nodes

Following is a timeline of this projects expected and actual development.

Ultimate Project Goal

Power-over-Ethernet (PoE Compute Nodes is a project to build compute node clusters containing multiple low-power System-on-Chip (SoC) devices and which can be powered over Gigabit network links from commodity managed Ethernet switches. The interface device will contain an FPGA or ASIC, a PoE Gigabit network interface and four or more USB2.0 Interface device ports configured to appear to host CPUs as USB Network interfaces.

Proof of Concept

The proof of concept involves utilising a NetFPGA board with 4 Gigabit network ports and a Xilinx FPGA with a bespoke NetFPGA USB 2 dual USB2.0 Interface module connected to two USB2.0 hosts, most likely Trim-Slice or Colibri T20 modules.

Dual USB2.0 Interface

The NetFPGA USB 2 dual USB2.0 Interface module interfaces to the 40-pin "debug" connector on the NetFPGA.

Design Interface

The NetFPGA 40-pin debug connector (J4) has 34 pins connected to the Virtex II chip - this can support up to two 12-signal ULPI devices.

Select USB2.0 Transceiver

The Cypress CY7C68003 ULPI USB2.0 Interface chip was chosen as the transceiver. Purchased from X-On Electronics.

Select PCB design software

The PCBs are to be fabricated by Seeed Studio, so the choice to use Eagle PCB design software was optimal for this supplier.

Learn Eagle

Eagle requires a schematic diagram to be created prior to PCB layout. There is a reasonable tutorial at SparkFun.

Design Board

The board design and custom library for the 24-pin QFN package are in SVN (where?)

Order Boards

Boards were ordered from Seeed Studio and delivered to ANU on or around 2012-01-18.

Build Interface

The interface module PCBs were manufactured by Seeed Studio in China. 10 double-sided PCBs were supplied. 24-pin CY7C68003 chips were soldered down using reflow soldering techniques at Research School of Engineering electronics lab.

Test Interface

A Papilio One development board with a Xilinx Spartan XC3S250E 250K gate FPGA device is used for performing electrical and software testing of the interface.

Familiarisation with Papilio

Select between Windows and Linux environment and install the Papilio downloader and test some pre-compiled bitstreams. Follow Getting Started

Configure Papilio Development Environment

Set up the Xilinx toolchain and test some simple codes. Follow Webpack VHDL Quickstart for the Papilio Platform

Develop some test USB2.0 code

We want to be able to check that the NetFPGA USB 2 interface can be enumerated and possibly also test some simple ping-pong USB2.0 transfers. Is it possible to implement the USB interface of an ATmega16U4 in the AVR Soft-CPU core? And then use LUFA or similar USB stack? What about using this?

Measure performance

How does the cluster perform when measuring performance against power consumption?