Rgmii io

rgmii_io is a Verilog module as part of the NetFPGA Reference Design framework and is responsible for converting the 4-pin Dual Data Rate (DDR) Reduced Gigabit Media Independent Interface (RGMII) signals from the Broadcom "QuadSquad" PHY into standard Gigabit Media Independent Interface (GMII) signals for further processing within the FPGA by the MAC etc.

The source code for the rgmii_io module is at $NF_ROOT/lib/verilog/core/nf2/generic_top/src/rgmii_io.v

rgmii_io is instantiated for each of the 4 Gigabit PHYs in the nf2_top module.

rgmii_io uses some FDDRRSE constructs to multiplex the data being transmitted out from the FPGA. For DDR data coming in, it simply uses both edges of the receive clock to clock in both halves of the data.