Rx queue

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rx_queue is a Verilog module and is part of the NetFPGA Reference Design framework. The source code for rx_queue is in $NF_ROOT/lib/verilog/core/io_queues/ethernet_queue/src/rx_queue.v and it is instantiated for each PHY by the nf2_mac_grp module.

rx_queue uses a pair of NetFPGA FIFOs, called:

  • gmac_rx_fifo (instantiated with coregen as "rxfifo_8kx9_to_72") and
  • pkt_chk_fifo (instantiated with coregen as "rxlengthfifo_128x13")


The FIFOs are responsible for operating in the dual clock domains (PHY rx clock, and system clock).

gmac_rx_fifo clocks in 9-bit data from the MAC (8-bit of PHY data + End-Of-Packet (EOP) bit) using the PHY rx clock and spits out 72-bit using the system clock. It can hold up to 8192 bytes of data which could be up to 128 packets.

pkt_chk_fifo contains one 13-bit entry per received packet with various status information in each entry. The existence of a packet in the fifos is indicated by this fifo being non-empty.