USB2 Net A

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USB2 Net A is a module that implements a USB 2 Network device in Verilog Hardware Description Language. It is released as Open Source/Creative Commons software.

USB2 Net A is designed to be compatible with the Linux drivers/net/usb/asix.c usbnet device driver.

It is responsible for implementing a ULPI interface at one end, and provide Ethernet MAC frames to upper-layer logic in the FPGA at the other end. It relies heavily on the OpenCores USB Function IP Core.

It is intended to be used by the NetFPGA USB 2 interface for providing 2 USB 2.0 network interfaces to the NetFPGA system.

Structure

To be compatible with the AX88178 and other ASIX USB 2 Ethernet interfaces/adapters, USB2 Net A will provide 5 endpoints:

  • Default Control IN (endpoint 0x80)
  • Default Control OUT (endpoint 0x00)
  • Interrupt IN (endpoint 0x81)
  • Bulk Data IN (endpoint 0x82)
  • Bulk Data OUT (endpoint 0x03)

The first three endpoints will be handled by logic within this module, probably without the use of a Soft CPU. The Bulk Data endpoints will deliver network packet data to/from a pair of FIFOs which will then make the packets available to other modules in the FPGA, such as a switching fabric as used in NetFPGA.