Difference between revisions of "NetFPGA USB 2 v0.2"
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# GNDs on J1 pins 1,2,21,22,39,40 | # GNDs on J1 pins 1,2,21,22,39,40 | ||
# general signals | # general signals | ||
| − | NET "u2i_reset" LOC = " | + | NET "u2i_reset" LOC = "AG16" | IOSTANDARD = LVCMOS33 ; # pin 3 |
| − | NET "u2i_status" LOC = " | + | NET "u2i_status" LOC = "AF16" | IOSTANDARD = LVCMOS33 ; # pin 4 |
# USB2 port 1 | # USB2 port 1 | ||
| − | NET "u2i_1_data< | + | NET "u2i_1_data<0>" LOC = "AJ15" | IOSTANDARD = LVCMOS33 ; # pin 15 |
| + | NET "u2i_1_data<1>" LOC = "AJ15" | IOSTANDARD = LVCMOS33 ; # pin 16 | ||
| + | NET "u2i_1_data<2>" LOC = "AJ15" | IOSTANDARD = LVCMOS33 ; # pin 17 | ||
| + | NET "u2i_1_data<3>" LOC = "AF14" | IOSTANDARD = LVCMOS33 ; # pin 18 | ||
| + | NET "u2i_1_data<4>" LOC = "AH13" | IOSTANDARD = LVCMOS33 ; # pin 5 | ||
| + | NET "u2i_1_data<5>" LOC = "AJ15" | IOSTANDARD = LVCMOS33 ; # pin 6 | ||
| + | NET "u2i_1_data<6>" LOC = "AG10" | IOSTANDARD = LVCMOS33 ; # pin 7 | ||
| + | NET "u2i_1_data<7>" LOC = "AH15" | IOSTANDARD = LVCMOS33 ; # pin 8 | ||
</pre> | </pre> | ||
Revision as of 13:02, 20 July 2012
NetFPGA USB 2 v0.2 is a dual USB 2 (480Mbps) adaptor for the NetFPGA 1G board. It is based on a pair of Cypress CY7C68013 EZ-USB2 (FX2LP) devices, one per channel.
The NetFPGA has a 40-pin "debug" connector with 6 grounds and 34 lines connected to the NetFPGA device.
Board
User Constraints File
Verilog (and other HDLs) use a User Constraints File (.ucf) to map physical pins of the FPGA to real signals. The mapping for the NetFPGA Debug connector is documented on that page. We now need to extend the mapping through to the CY7C68013 devices on the interface board.
# NetFPGA USB 2 interface pin definitions # GNDs on J1 pins 1,2,21,22,39,40 # general signals NET "u2i_reset" LOC = "AG16" | IOSTANDARD = LVCMOS33 ; # pin 3 NET "u2i_status" LOC = "AF16" | IOSTANDARD = LVCMOS33 ; # pin 4 # USB2 port 1 NET "u2i_1_data<0>" LOC = "AJ15" | IOSTANDARD = LVCMOS33 ; # pin 15 NET "u2i_1_data<1>" LOC = "AJ15" | IOSTANDARD = LVCMOS33 ; # pin 16 NET "u2i_1_data<2>" LOC = "AJ15" | IOSTANDARD = LVCMOS33 ; # pin 17 NET "u2i_1_data<3>" LOC = "AF14" | IOSTANDARD = LVCMOS33 ; # pin 18 NET "u2i_1_data<4>" LOC = "AH13" | IOSTANDARD = LVCMOS33 ; # pin 5 NET "u2i_1_data<5>" LOC = "AJ15" | IOSTANDARD = LVCMOS33 ; # pin 6 NET "u2i_1_data<6>" LOC = "AG10" | IOSTANDARD = LVCMOS33 ; # pin 7 NET "u2i_1_data<7>" LOC = "AH15" | IOSTANDARD = LVCMOS33 ; # pin 8
