Verilog

Verilog is a Hardware Description Language, similar to VHDL. It is used for ASIC and FPGA Electronic Design Automation (EDA)

"Verilog is patterned after "C""..."Verilog is terse and doesn't take its type-checking seriously" - Johan Sandstrom.

Uses

Verilog is used exclusively by the NetFPGA project as well as by many Opencores projects.

Tips

ERROR:Xst:518

ERROR:Xst:528 - Multi-source in Unit ... on signal ...; this signal is connected to multiple drivers.
Drivers are:
   Output signal of ...
   Output signal of ...

This error is generally caused by a signal being driven by more than one "always" block.

More information at: Xst:528 - Multi-source in Unit on signal;...

Icarus Verilog

Icarus Verilog is a FOSS Verilog simulator which can compile Verilog input files into a range of outputs, including .vvp files for simulating on the accompanying vvp simulator. Some links:

• Getting Started with iverilog
• GTKWAVE and using it with iverilog

External Links

• Verilog at Wikipedia
• CSCI 320 Computer Architecture Handbook on Verilog HDL
• Comparing Verilog to VHDL Syntactically and Semantically by Johan Sandstrom
• Compile Your C code into Verilog from c-to-verilog.com
• ISE 11 In-Depth Tutorial from Xilinx
• Verilog Tutorial from ASIC-World.com
• How to write FSM in Verilog? from ASIC-World.com
• Procedural Timing Control from ASIC-World.com
• Task And Function from ASIC-World.com
• Verilog at fullchipdesign.com
• RAM Modelling in Verilog
• Verilog Tutorial from Princeton University
• Xilinx Tools Tutorial Lab notes from MIT 6.111
• Verilog by Example
• Verilog Simulation Guide from Actel.com
• v2html The Verilog to html converter
• Using Xilinx Tools in Command-Line Mode from outputlogic.com
• Verilog Examples at rose-hulman.edu
• Verilog Frequently Asked Questions
• Verilog-2001 Quick Reference Guide from sutherland-hdl.com

(note for Bob: see also: ~/Papers/Verilog.pdf)