Difference between revisions of "NetFPGA USB 2 v0.2"
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* [http://gnosia.anu.edu.au/Docs/NetFPGA_USB_2_v02.pdf schematic] (produced with [[Eagle]]) | * [http://gnosia.anu.edu.au/Docs/NetFPGA_USB_2_v02.pdf schematic] (produced with [[Eagle]]) | ||
| + | ==Parts== | ||
| + | * | ||
| + | * 3 x Bivar SMD 1204 RG LED (X-On p/n SM1204BC-R/G) (datasheet ([http://gnosia.anu.edu.au/ReferenceDocs/Bivar/SM1204BC_RG.pdf local copy])). | ||
| + | |||
| + | ==Testing== | ||
| + | The board can be tested without needing to be connected to a [[NetFPGA 1G]] by adding a suitable 3.3V regulator to pick up the 5.0V from the USB connector and supplying VCC (3.3V) to the on board circuitry. | ||
| + | |||
| + | A suitable 3.3V regulator is the TI/NatSemi LM3940 (available from [[Jaycar Electronics]]) (datasheet ([http://gnosia.anu.edu.au/ReferenceDocs/Texas_Instruments/lm3940.pdf local copy])). | ||
==User Constraints File== | ==User Constraints File== | ||
[[Verilog]] (and other HDLs) use a User Constraints File (.ucf) to map physical pins of the FPGA to real signals. The mapping for the [[NetFPGA]] Debug connector is documented on that page. We now need to extend the mapping through to the [[CY7C68013]] devices on the interface board. | [[Verilog]] (and other HDLs) use a User Constraints File (.ucf) to map physical pins of the FPGA to real signals. The mapping for the [[NetFPGA]] Debug connector is documented on that page. We now need to extend the mapping through to the [[CY7C68013]] devices on the interface board. | ||
Latest revision as of 11:42, 9 August 2012
NetFPGA USB 2 v0.2 is a dual USB 2 (480Mbps) adaptor for the NetFPGA 1G board. It is based on a pair of Cypress CY7C68013 EZ-USB2 (FX2LP) devices, one per channel.
The NetFPGA has a 40-pin "debug" connector with 6 grounds and 34 lines connected to the NetFPGA device.
Contents |
Board
Parts
- 3 x Bivar SMD 1204 RG LED (X-On p/n SM1204BC-R/G) (datasheet (local copy)).
Testing
The board can be tested without needing to be connected to a NetFPGA 1G by adding a suitable 3.3V regulator to pick up the 5.0V from the USB connector and supplying VCC (3.3V) to the on board circuitry.
A suitable 3.3V regulator is the TI/NatSemi LM3940 (available from Jaycar Electronics) (datasheet (local copy)).
User Constraints File
Verilog (and other HDLs) use a User Constraints File (.ucf) to map physical pins of the FPGA to real signals. The mapping for the NetFPGA Debug connector is documented on that page. We now need to extend the mapping through to the CY7C68013 devices on the interface board.
# NetFPGA USB 2 interface pin definitions # GNDs on J1 pins 1,2,21,22,39,40 # general signals NET "u2i_reset" LOC = "AG16" | IOSTANDARD = LVCMOS25 ; # pin 3 NET "u2i_status" LOC = "AF16" | IOSTANDARD = LVCMOS25 ; # pin 4 # USB2 port 1 NET "u2i_1_data<0>" LOC = "AJ15" | IOSTANDARD = LVCMOS25 ; # pin 15 NET "u2i_1_data<1>" LOC = "AJ15" | IOSTANDARD = LVCMOS25 ; # pin 16 NET "u2i_1_data<2>" LOC = "AJ15" | IOSTANDARD = LVCMOS25 ; # pin 17 NET "u2i_1_data<3>" LOC = "AF14" | IOSTANDARD = LVCMOS25 ; # pin 18 NET "u2i_1_data<4>" LOC = "AH13" | IOSTANDARD = LVCMOS25 ; # pin 5 NET "u2i_1_data<5>" LOC = "AJ15" | IOSTANDARD = LVCMOS25 ; # pin 6 NET "u2i_1_data<6>" LOC = "AG10" | IOSTANDARD = LVCMOS25 ; # pin 7 NET "u2i_1_data<7>" LOC = "AH15" | IOSTANDARD = LVCMOS25 ; # pin 8
