Nf2 core
From Bobs Projects
nf2_core is a Verilog module in the NetFPGA Reference Design framework that "glues" all other major modules together.
Contents |
I/Os
nf2_core contains I/O definitions for the main Xilinx Virtex-II FPGA on NetFPGA 1G:
- 4 x Gigabit Ethernet PHYs, connected using Gigabit Media Independent Interface (GMII)
- CPCI (Spartan FPGA PCI controller to CPU)
- Static RAM (SRAM) 1 & 2
- Dual Data-Rate (DDR2) Dynamic RAM
- DMA to PCI (via CPCI)
- CPCI debug data
- MDC/MDIO interface
- CPCI/Spartan configuration/re-programming pins
- core clock
- reset
Modules
The "standard" NetFPGA Reference Design framework modules instantiated in nf2_core are:
- nf2_mac_grp (0 - 3) - the Ethernet MAC group modules
- cpu_dma_queue (0 - 3) - the CPU DMA queues (over the PCI)
- cpci_bus
- sram_arbiter
- user_data_path
- nf2_reg_grp
- reg_grp - multiple
- device_id_reg
- nf2_mdio
- nf2_dma
- unused_reg - multiple
Modifications
NetFPGA USB 2
The nf2_core module is modified for the NetFPGA USB 2 v0.3 firmware to replace the "debug" Logic Analyser (LA) connector definition with the NetFPGA USB 2 v0.3 interface and associated nf2_usb2 module.
